Influence Of Concentration And Fill Depth On Product Resistance Of Sucrose During Freeze Drying
The objective of the study described in this article was to characterize product resistance as a function of dry layer thickness for various sucrose solutions using SMART Freeze-Dryer technology. This new approach employs manometric temperature measurement (MTM) for the optimization of a lyophilization process during the first laboratory experiment. Submitted by FTS Systems
Cabasse Tweeter Membrane Selects APTIV Films The Highest Performing Melt Processable Polymer
Cabasse, a French manufacturer and pioneer of high efficiency loudspeakers, has selected Victrex APTIV film – made using VICTREX PEEK polymer, widely considered to be the highest performing melt processable polymer available – for use in the tweeter diaphragm of its La Sphere speaker system
The Impact Of TOC In UPW Systems For The Electronics Industry
During the past four decades the electronics industry has exponentially increased the number of circuits that are etched onto silicon chips. The
increase in the number of circuits has significantly decreased the line-widths. Thereby, increasing by magnitudes the requirements for accurate and continuous measurement of the UPW system...
Microsemi Adds CLASS-E Reference Design Kit For 1000 W RF Generators
Microsemi Corporation has introduced a new solid state 1KW, Single-Ended, CLASS-E reference design kit based on Microsemi’s DRF1200 Driver/MOSFET hybrid
Test Structure Design For Parallel Testing
Parallel testing provides higher throughput than conventional sequential testing. Although parallel testing can sometimes be performed successfully on existing test structures, efficient test execution without signal loss generally requires attention to various test structure details. Frequently, optimizing the test structures for parallel test will increase throughput significantly and improve measurement integrity
Getting Started In Parallel Test -- Modification Of Existing Scribe Line TEGs
By Randall G. Lee, Keithley Instruments, Inc.
Wafer-level parallel parametric testing involves concurrent execution of multiple tests on multiple scribe line test structures. This has the potential for huge improvements in throughput with existing test hardware
Advances In Instrumentation Used To Monitor High-Purity Water Treatment Systems
High-purity water treatment technology has progressed and changed significantly in recent years. Major trends include the wider variety of membrane processes driving an increasing share of purification, more use of reclaimed and recycled water, and treatment systems with more user-friendly interface.
Submitted by Mettler-Toledo Thornton
Implementation Of Wafer Level Parallel Test
By Randall G. Lee, Keithley Instruments, Inc.
Parallel parametric test is an emerging strategy for wafer-level testing that involves concurrent execution of multiple tests on multiple scribe line test structures. It offers a relatively inexpensive way to increase throughput, thereby lowering the cost of ownership (COO) significantly. Just as important, as device scaling increases the randomness of failures, parallel testing can address the growing need to perform more tests on the same structures in less time. In this case, users can choose to either increase the number of tests performed at each site, or increase the number of sites
Parallel Parametric Measurements Reduce Test Costs
By Randall Lee, Keithley Instruments, Inc.
As the dimensions of modern integrated circuits continue to shrink, device fabrication and parametric testing have become more challenging. Every device shrink, process innovation, and new material makes the volume and repeatability of parametric test data more critical in process development and the control of modern fabs. Today’s fabs must understand how to produce and characterize advanced materials such as high-K gate dielectrics and low-K insulators used in conductive layers – quickly and cost-effectively. Tomorrow’s IC producers may need to manufacture and test transistors formed from carbon nanotubes or other technologies that researchers have just begun to explore.
Silicon Image Licenses Impinj's AEON/MTP Nonvolatile Memory For High-Volume Consumer Electronics And Computing Chips
Leading logic nonvolatile memory (NVM) intellectual property (IP) supplier, Impinj, Inc., recently announced that Silicon Image, a leading provider of semiconductors for the secure storage, distribution and presentation of high-definition content, has licensed Impinj's AEON NVM cores to embed system-critical application data in high-definition multimedia interface (HDMI) and serial advanced technology attachment (SATA) chips.