This article is the third part of the four-part series. To read the first part, click here.
Wafer-level parallel parametric testing involves concurrent execution of multiple tests on multiple scribe line test structures. This has the potential for huge improvements in throughput with existing test hardware.
For many fabs or test cells with mature processes, the most attractive approach to parallel test is to change only the test sequencing on existing TEGs. This approach is usually the best way to achieve significant throughput improvements with a relatively limited investment in analysis, new software, and test sequence modifications. Typically, the process starts with analysis of the TEG and test sequence to find a way to minimize switching time between test pads. Generally, this involves the reordering or regrouping of existing tests on heterogeneous structures.
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Article: Getting Started In Parallel Test -- Modification Of Existing Scribe Line TEGs
This article is the third part of the four-part series. To read the fourth part, click here.