Parallel Parametric Measurements Reduce Test Costs

As the dimensions of modern integrated circuits continue to shrink, device fabrication and parametric testing have become more challenging. Every device shrink, process innovation, and new material makes the volume and repeatability of parametric test data more critical in process development and the control of modern fabs. Today's fabs must understand how to produce and characterize advanced materials such as high-K gate dielectrics and low-K insulators used in conductive layers – quickly and cost-effectively. Tomorrow's IC producers may need to manufacture and test transistors formed from carbon nanotubes or other technologies that researchers have just begun to explore.

Parallel Test Practices
By way of definition, wafer-level parallel parametric testing involves concurrent execution of multiple tests on multiple scribe line test structures. It offers enormous potential for increasing the throughput of existing test hardware.

Increasing market pressures are driving fabs to minimize test times and explore the benefits of parallel testing. This methodology offers a relatively inexpensive way to increase test throughput with existing parametric test systems, thereby lowering significantly the cost of ownership and total cost of testing. Just as important, parallel testing can address the growing need to perform more tests on the same structures in less time as device scaling increases the randomness of failures. By extracting more data from every probe touchdown, parallel test offers fabs the flexibility to choose whether they want to increase their wafer test throughput dramatically, or use the available time to acquire significantly more data and thereby gain greater insight into production processes.