Test Structure Design For Parallel Testing

This article is the fourth part of a four-part series. To read the first part, click here.

Parallel testing provides higher throughput than conventional sequential testing. Although parallel testing can sometimes be performed successfully on existing test structures, efficient test execution without signal loss generally requires attention to various test structure details. Frequently, optimizing the test structures for parallel test will increase throughput significantly and improve measurement integrity.

Common Substrate Issues

The semiconductor wafers produced in most processes have a common substrate. (Wafers produced by dielectric isolation processes are an exception.) Wells with a polarity opposite to that of the substrate are isolated—for example, separate n-doped wells in a p-doped substrate produced by a CMOS process. However, wells having a polarity identical to that of the substrate—for example, p-doped wells in a p-doped substrate are all shorted together. As a result, simultaneously forcing different voltages at different points can introduce significant errors as a result of:

• Different voltages causing current flow and a voltage gradient across the substrate.
• The voltage gradient causing uncertainty about exact substrate voltages under the gates of transistors under test.

Parasitic Voltage-drop Issues

Semiconductor test structures are generally much smaller than the probe pads used to connect the tester to these structures. As a result, the total area dedicated to a test structure is roughly the same as the area occupied by its probe pads. Understandably, during test structure design, substantial effort is devoted to minimizing the number of probe pads.