Virage Logic Expands Silicon Aware IP Offering With 65-Nanometer Memory And Logic Products
The SiWare Memory product line provides a powerful dashboard that enables SoC designers to explore the tradeoffs between performance, area, power and statistical yield to generate optimal memory configurations. This "dashboard control" capability is critical at 65nm where design and process complexities require sophisticated management of the various tradeoffs in order to effectively meet stringent end-product requirements and increasingly narrow market windows. (Virage Logic also today announced new Silicon Aware memory test and yield analysis products. See related press release titled, "Virage Logic Broadens its Silicon Aware IP Offering with New Release of the STAR Memory System.")
In addition to being optimized for design-for-manufacturing (DFM), the SiWare Logic product line offers SoC designers the ability to manage tradeoffs between area, speed and power. The SiWare Logic library architectures – high-speed, high-density and ultra-high-density – can also be extended with ultra-low-power (ULP) kits for power management and engineering change order (ECO) kits for metal-only design modifications.
"Since the first introduction of our 65nm offering with TSMC, UMC and Freescale in 2004, we have leveraged our early experience to provide designers with an advanced product offering that addresses tough 65nm challenges," said Brani Buric, vice president of product marketing and strategic foundry relationships at Virage Logic. "Our SiWare Memory and SiWare Logic offerings incorporate what we've learned to provide a rich set of performance-enhancing, area-saving, power-optimizing and yield-accelerating options for SoC designers to control as they develop competitive products."
"Our successful, long-standing relationship with Virage Logic spans various process technologies for multiple foundries, and enables us to utilize their portfolio of highly differentiated IP solutions in our industry-leading multi-mode VDSL2 and gateway products," said Shekhar Khandekar, vice president of operations at Ikanos. "As a result, our products are able to power the processing and distribution of triple play services in the carrier infrastructure and at the customer premise."
"Virage Logic was one of the pioneers in establishing the third-party commercial IP market more than 10 years ago and they have a long track record of being first to deliver quality, silicon proven products on each new node," said Rich Wawrzyniak, senior analyst at SEMICO Research Corporation. "I am impressed with the breadth of their new 65nm SiWare Memory and SiWare Logic offering and the attention to detail in terms of providing a complete capability set. With the ability to manage and optimize speed, power, area and yield tradeoffs, the SiWare product family enables designers to successfully address the challenges of 65nm design."
About SiWare Memory Compilers and SiWare Logic Libraries
The SiWare Memory product line of silicon aware compilers provides power-optimized memories for advanced processes at 65nm. These high-performance memory compilers minimize both static and dynamic power consumption and provide optimal yields. SiWare High-Density memory compilers are optimized to generate memories with the absolute minimum area. SiWare High-Speed memory compilers are designed to help designers achieve the most aggressive critical path requirements. Compile-time options for process threshold variants, power saving modes, read and write margin extensions, ultra-low voltage operation, and innovative design for at-speed test enable SoC designers to configure optimal solutions for their specific design requirements.
The SiWare Logic product line includes yield-optimized standard cells for a wide variety of design applications at 65nm with multiple threshold process variants. SiWare Logic libraries are offered using three separate architectures to optimize circuits for Ultra-High-Density, High-Speed, or general use. SiWare Ultra-Low-Power extension libraries provide designers with the most advanced power management capabilities.
About Silicon Aware IP
To help SoC designers address the complex predictability and manufacturability challenges at advanced process nodes, in 2005 Virage Logic pioneered a new class of semiconductor IP called Silicon Aware IP. The company's Silicon Aware IP offering (embedded memories, logic libraries and I/Os) includes silicon behavior knowledge for increased predictability and manufacturability. This intelligence includes hardware implementations for optimal yield in the design phase and extends to include test, repair, and diagnostics for manufacturability. Because Silicon Aware IP understands the behavior of silicon and is able to address post-silicon issues, it is key in helping designers maximize yield, lower test escapes, increase reliability, speed time-to-volume and improve overall manufacturability.
SOURCE: Virage Logic Corporation