Virage Logic Delivers Memory Compiler And Logic Library For TSMC 40nm Process
The SiWare product line, first introduced in October 2007 for the 65nm process, addresses the increasingly complex design requirements placed on physical IP at advanced process nodes. The SiWare Memory compilers and SiWare Logic libraries provide designers with a complete "dashboard" of options for maximum flexibility in effectively managing design tradeoffs to meet their specific requirements.
As the first commercial IP provider with memory compiler and logic library IP in use on TSMC's 40nm process, Virage Logic offers customers early access to design more competitive chips at reduced risk while helping enable them to take advantage of significant cost savings. Primary end markets for SiWare IP on TSMC's 40G process include computer, graphics, networking and storage applications, while primary end markets for SiWare IP on TSMC's 40LP process include wireless, battery-operated and consumer applications. With its advanced tradeoff capabilities, SiWare Memory users can achieve static power savings of up to 35 percent, 70 percent and 90 percent depending on their selection of the built-in light sleep, deep sleep and shut-down modes available in both the 40G and 40LP memories.
Building on the tradeoff capabilities introduced in the 65nm SiWare product line to enable optimal management of performance, area, power and statistical yield, the 40nm SiWare offering includes advanced built-in power management capabilities that will enable designers to mitigate high power consumption at this advanced process node.
"With the SiWare 40nm announcement, our customers can benefit by taking advantage of Virage Logic's IP products to help differentiate their semiconductor products from competitive offerings with respect to speed, area, power management, standby power and yield," said Brani Buric, vice president of product marketing and strategic foundry relationships at Virage Logic. "Virage Logic's broad IP portfolio and extensive silicon validation program enables our customers to reduce design risk, shorten time-to-market and time-to-volume, and lower their development costs. Virage Logic IP provides an exceptional value for customers by offering complete product and service packages – from small and large projects, to serving as a full, corporate-wide IP partner."
"Virage Logic has a long track record of being first to deliver quality, silicon proven products on each new node," said Rich Wawrzyniak, senior analyst at Semico Research. "The company's new 40nm SiWare offering shows attention to detail in terms of providing a built-in power management solution for SoC designers. With the ability to manage and optimize speed, power, area, and yield tradeoffs, the robust SiWare products enable designers to successfully address the complex challenges of 40nm design. Virage Logic's technology leadership position should provide customers a solid future in investing at 40nm."
About SiWare Memory Compilers and SiWare Logic Libraries
The SiWare Memory product line of silicon aware compilers provides power-optimized memories for advanced processes. These high-performance memory compilers minimize both static and dynamic power consumption and provide optimal yields. SiWare High-Density memory compilers are optimized to generate memories with the absolute minimum area. SiWare High-Speed memory compilers are designed to help designers achieve the most aggressive critical path requirements. Compile-time options for process threshold variants, power saving modes, read and write margin extensions, ultra-low voltage operation, and innovative design for at-speed test enable SoC designers to configure optimal solutions for their specific design requirements. All SiWare memories are fully supported by Virage Logic's STAR Memory System, the company's flagship integrated embedded memory test and repair system. For repair purposes, the STAR Memory System deploys foundry-developed eFuse for repair signature storage. The STAR Memory System employs test algorithms tailored for advanced processes for higher product reliability and accelerated time-to-yield.
The SiWare Logic product line includes yield-optimized standard cells for a wide variety of design applications at 40nm with multiple threshold process variants. SiWare Logic libraries are offered using three separate architectures to optimize circuits for Ultra-High-Density, High-Speed, or general use. SiWare Ultra-Low-Power extension libraries provide designers with the most advanced power management capabilities.
SOURCE: Virage Logic Corporation