Viewlogic to Support Xilinx Virtex Architecture

Viewlogic Systems, Inc. this week announced support of the new Xilinx Virtex family in their Workview Office and Powerview suite of products.

IntelliFlow, Viewlogic's FPGA design manager, will provide Virtex designers with a custom set of flows for this architecture. The designer will be able to enter their design as a mixture of gates, language and/or state diagrams and target any of the Virtex parts that are available. Via IntelliFlow, the designer has a single point of entry for functional simulation, synthesis, place and route, timing verification, board level symbol/model creation and programming file generation. Full control of the upcoming Xilinx Alliance 1.4 place and route software will be available. A downloadable web service pack of the IntelliFlow, Virtex integration is scheduled to be available for all Workview Office customers in Q1, 1998.

Designers who use a language-based design methodology will have the choice of the VCS Verilog simulator or SpeedWave VHDL simulator for verification. Both of these simulators accept post place and route netlists generated by the Xilinx Alliance place and route software for Virtex designs.

According to a spokesman for Viewlogic, high performance FPGAs like those in Virtex are pushing FPGA designers to adopt an ASIC-like design methodology. Unlike the ASIC designer, the FPGA designer is often responsible for the design and verification of the PCB as well. Viewlogic's systems will enable designers to design and verify the FPGA in one environment, both individually and as part of the larger system, the company said.

For more information: Viewlogic Systems, Inc., Karen Wills, Tel: 508-480-0881