Product/Service

Subwavelength IC Design Sign-Off Tool

Source: Numerical Technologies Inc.
The company offers the SiVL, a new integrated circuit (IC) design-to-manufacturing tool that verifies the layout of a subwavelength IC against the silicon it is intended to produce.
The company offers the SiVL, a new integrated circuit (IC) design-to-manufacturing tool that verifies the layout of a subwavelength IC against the silicon it is intended to produce. The company expects that SiVL will soon be used as the final step in every subwavelength design flow to produce "silicon sign-off files" that semiconductor companies use to produce a chip.

Subwavelength ICs are designed with features that are smaller than the wavelength of the optical source used to produce them. As a result, the features become unpredictably distorted during the manufacturing process, adversely impacting yield and performance.

SiVL Capabilities and Methodology
Central to the SiVL technology is a fast, accurate silicon simulation engine that considers the lithography and etch characteristics of the specific process that will be used during manufacturing. SiVL is a critical part of the subwavelength design-to-manufacturing flow. The same technology and process model are supported through the design to manufacturing flow, with support from the company's Virtual Stepper.

SiVL may also be used to determine whether a design needs Optical Proximity Correction (OPC), define where and how much OPC will be needed, and evaluate whether the OPC worked all to ensure that the design will print properly in silicon, with predictable yield and high performance. Traditionally, OPC tools have applied OPC everywhere, resulting in huge photomask files and a photomask that has a long turnaround time, is very expensive and is difficult to manufacture.

Running SiVL before and after applying OPC reduces mask complexity, ensuring faster turnaround times, less expensive mask sets and higher yields. SiVL performs silicon vs. layout verification, in contrast to other physical verification tools that apply OPC and then simply check design rules (DRC) or perform layout vs. schematic (LVS) verification. Because DRC and LVS do not take into account any OPC that may have been performed on the design, they cannot assure that the silicon will match the layout. Running SiVL as a final check, companies can be assured before silicon is manufactured that OPC works, and that their end silicon will accurately reflect the layout.

Phase Shifting Also Integrated
Companies who need the extra performance and yield boost that phase-shifting brings will be able to use the SiVL models, technology and methodology with NumeriTech's iN-Phase phase-shifting solution announced in May 1999.

Numerical Technologies, Inc., 70 W. Plumeria Dr., San Jose, CA 95134. Tel: 408-919-1910. Fax: 408-919-1920.