StateCAD is a universal graphical front end to all major HDL (VHDL, Verilog, Altera-HDL, Abel HDL and C) synthesis and simulation tools. It provides design entry, automatic debug, optimization, HDL generation and documentation of state machines and digital logic. StateCAD 30 Day Eval is 100% equivalent to its Commercial Edition for thirty days from installation. It also includes StateSIM, for graphical
simulation, interactive debug and automatic test bench generation.