SOI Wafer Fabrication Process

The SiGen SOI wafer fabrication process is based on NanoCleave and other novel manufacturing technologies that allow for cost-effective SOI wafer fabrication with exceptional material quality and yield. SiGen's SOI wafer fabrication process has up to 40% fewer steps than competing SOI wafer schemes. This technology also provides a pathway to production of ultra-thin SOI layers (with Si thickness of less than 200Å) and advanced, high-mobility materials such as SiGe alloys.

Wafer Quality
SiGen's SOI wafers are free of defects that limit the yield of older SOI technologies. The device silicon and buried oxide layers are well within the 5% thickness uniformity range normally specified for device fabrication. The Atomic Layer Cleaving process provides exceptional wafer-to-wafer and lot-to-lot control of layer thickness since no post-cleaving Chemical Mechanical Polishing (CMP) and edge smoothing are needed.

Cost Advantages
The directness and simplicity of the SiGen NanoCleave process provides readily transferable and scalable SOI production technology. In high-volumes, the expected cost savings range from 50% to 70%. The extension of the NanoCleave tool-set to 300mm wafers brings even greater economic advantages, especially with the use of high-productivity tools such as SiGen's PIII systems.

Silicon Genesis Corporation (SiGen), 590 Division Street, Campbell, CA 95008. Tel: 408-871-3939; Fax: 408-871-8607.