Shallow Junctions Become Reality

The benefits of transistor scaling motivate the semiconductor industry's continual reductions in feature size. As channel length decreases, switching speed increases. In order to scale device density with channel length, the source and drain junctions must shrink, too.

The wiring to the channel—interconnect, contact, and junction—must have lower resistance than the channel itself. Yet, as the junction cross section decreases, resistance increases. To offset this effect, the source and drain implant dose and activation must increase. The Semiconductor Industry Association's (SIA; San Jose, CA) Roadmap calls for drain junction depth to drop from 75 nm for the 0.25 µm generation to 30 nm for the 0.10 µm generation, as dopant concentration increases from 4-6 x 10¹⁷ to 2-3 x 10¹⁸. Once an implant is in place, keeping the dopant atoms in position is a challenge. The high temperatures used to force atoms into the crystal lattice during dopant activation also encourage dopant diffusion, increasing junction depth (see a related article).

According to Israel Beinglass, thermal process and implant product manager at Applied Materials (Santa Clara, CA), the company's new ultrashallow junction process module solves both implant and annealing problems. For the first step, Beinglass said, the xR LEAP ion implant system's patented lens design achieves more parallel beams and higher beam currents at the very low energies (200eV to 2 keV) required.

Dopant activation has a higher activation energy than dopant diffusion [1], but occurs more quickly once the activation energy is reached. Therefore, higher annealing temperatures for shorter times maximize dopant activation (minimizing sheet resistance) while reducing diffusion. Furnace anneals, which have relatively slow ramp rates and long soak times at the process temperature, allow significant dopant diffusion. Rapid thermal annealing (RTA) reaches the process temperature in seconds, rather than minutes.

Even among different RTA processes, Beinglass explained, the process ramp rate affects the junction behavior. A spike anneal, in which the wafer is heated to process temperature as rapidly as possible and then allowed to cool, gives shallower junctions for a given sheet resistance than a soak anneal, in which the wafer is held at temperature for a few seconds.

Click here to see graph.

A 75 °C/sec ramp is best, Beinglass said. Higher ramp rates have little effect on the junction, while increasing wafer slip. The rapid temperature ramps required by spike anneals require excellent temperature uniformity. Non-uniform temperatures can warp the wafer and cause junction resistance variations. The ultrashallow junction module relies on the RTP Centura system's multipoint, closed-loop, emissivity-independent temperature control.

References
[1] E. G. Seebauer and R. Ditchfield, "Fixing hidden problems with thermal budget," Solid State Technology, p.111 (October, 1997).
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By Katherine Derbyshire

For more information: Applied Materials. 3050 Bowers Ave. Santa Clara, CA, 95054-3299. Tel: 408-727-5555.