Re-Engineering ASIC Design With LPGA
Meir Janai, Chief Scientist, Chip Express Corporation
Contents
Laser programmable gate-arrays (LPGAs) of over 100k gates which can be economically produced within a few hours simplify the design cycle and shorten the time-to-market of systems incorporating gate arrays. This paper discusses the technological background and architecture of LPGAs, and describes the transfer from design to volume production.
Laser programmable logic devices were proposed over 20 years ago (1), but only recently high density laser programmable random logic devices have come of age (2). Previous attempts to produce high density LPGAs have failed because of low laser processing yield and because of the relatively large diameter of each programming point. For any useful purpose, the diameter of a laser programming point in an LPGA should be equal to or smaller than the diameter of a via grid point of the corresponding IC technology. The LPGAs described below achieve these densities.
LPGAs allow rapid production, testing, debugging and verification of ASIC designs in an environment that closely resembles the final product. Pins, functions and performance are compatible with the final device.
The first part of this paper describes the technology and the architecture of second generation double-metal LPGAs and of third generation triple-metal LPGAs. Third generation LPGAs incorporate a new gate array architecture which gives higher speed, higher drive and lower power consumption than the traditional double input NAND cell-based gates of second generation LPGAs.
The second part describes the potential implications of these technologies for ASIC design. Fast breadboarding of complex ASIC devices may shift the design methodology from heavy dependence on component simulation to more risk-taking, faster-turn ASIC acquisition, allowing relatively more design flexibility, earlier system testing, more efficient debugging and earlier software development.
Double metal LPGA (back to top)
Double-metal LPGAs are similar to standard channeled gate arrays with a double input NAND cell. In the LPGAs of Chip Express all transistors, both metal layers, and all the potential contacts and vias are pre-fabricated (3).
To program the device, a cut-only technology removes all the undesired metal for a specific application. Both metal layers can be programmed by the laser. Any via which is redundant for a given design can be separated from the metal grid by cutting the adjacent metal strips. Because the technology cuts, but does not deposit, metal, the specific resistivity of the remaining metal lines is identical to that of standard mask-programmable gate arrays (MPGAs), improving performance and simplifying modeling. A design which was prototyped by laser can be transferred to high volume MPGA production with negligible change in performance.
Laser cutting can configure the logic modules to produce a full set of macrocells of a typical gate array library. Each 2 input NAND cell needs about 50 laser programming points to implement the library. Twenty-four tracks per channel gives a total of 170 cut points per gate. Additional cut-points for configuring the I/Os bring a 100k gate LPGA chip to about 20,000,000 laser cut points.
Triple metal LPGA (back to top)
The triple metal LPGAs of Chip Express incorporate complex logic cells. The logic cells have 8 inputs each, and they are function selectable. Each cell comprises three multiplexers of different sizes and an AND gate. These new cells combine some basic concepts used in the development of FPGA logic cells with the routing flexibility of standard gate arrays. There are a few other important distinctions between double metal and triple metal LPGAs:
- The triple-metal LPGA structure is basically a "sea of logic cells." All silicon area is densely packed; the cells are implemented in poly and metal 1, and all routing is in metal layers 2 and 3. This structure increases the gate density by another factor of 2 over the channeled structure in double-metal LPGAs.
- The power and ground were moved from the upper to the lower metal layer, to free the space for laser programmable routing.
- Stacked vias and contacts bring the power and ground to the upper surface for connection to the cell inputs, where needed.
Transistor sizes in the complex logic cells were varied and optimized. A complex logic cell which occupies the area of 2 double input NAND cells in the previous architecture has the equivalent logic power of 4 double input NAND cells, with higher speed and lower internal power consumption. Yet the complex cell achieves a high output drive by using a relatively wide transistor in the final multiplexer stage.
When designing for triple metal LPGAs, synthesis must be used. Initial experiments using commercial synthesis tools have given a utilization of 75% of the cells.
The LPGAs described above can be programmed by one of three technologies: laser cutting, OneMask programming, or volume production.
Laser Cutting (back to top)
Laser cutting is done by the QS650 system manufactured by Chip Express (Israel) Ltd. These systems use a pulsed, frequency doubled Nd: YAG laser at pulse repetition rates of about 10,000 Hz. Laser energy is stabilized to within 5%. An interferometric controlled stage combined with an automatic alignment and registration system control the pulse position and pulse dimension to 0.15 micron. The system operates on single, unpackaged dies. The stage carrying the dies is enclosed in a class 100 environmentally controlled compartment.
The lower metal level to be cut is accessed through special windows opened in the intermetal dielectric layer in the prefabricated wafer.
The system can process about 1 die per hour.
OneMask Programming (back to top)
The OneMask technology is a standard photo-lithographic process in which photoresist is applied over the upper metal grid and over the windows in the inter-metal dielectric layer. A single mask exposes all metal segments to be removed, and a single etch process clears both the upper and the underlying metal layer segments. This process is efficient for production of small quantities (100 to 5000 dice).
Volume Production (back to top)
Volume production uses interconnect masks as for standard gate-arrays with all unwanted metal segments removed from the data.
The different production options become economical depending on the quantity of parts needed, and they are all compatible in performance.
Design
flow and transfer to manufacturing
The design flow of LPGAs follows standard procedures for gate arrays:
- Netlist formation by Synopsys, Viewlogic, Mentor etc.
- Functional & timing verification by any of the above or Verilog
- Test vector generation
- Layout
- Post-layout simulation
- Laser prototyping
- If approved for production - Fast/Slow prototype chips (optional)
- Pre-production run by OneMask
- High volume production.
Since the cost of step (6) is relatively low—no tooling needs to be made—and since the cost of iteration is also low, steps (2), (3) & (5) may not require intensive work. Sign-off requirements are reduced, partial test-vectors are sufficient for the preliminary run and the designer can move forward to system evaluation.
For >30K gate devices this approach shortens the average design cycle of a system by more than 1 month.
Discussion (back to top)
The common practice of ASIC design relies heavily on simulation. Since most IC prototypes are made by equipment and systems designed for mass production, the cost-of-error is high. Manufacturers avoid the costly process of prototype manufacturing until certain that the design is correct and debugged. Even if prototypes can be made within three days by a fast line in a conventional fab, the strict requirements for sign-off delay the run by a few weeks. A prototyping system which costs only 1% of the cost of a fully equipped fab, with relatively small variable costs, reduces the cost-of-error significantly.
Fully equipped fabs which produce prototypes for their customers do it only because they assume that a large order will follow. Prototyping by itself is not economical for a mass production facility with high operation costs and heavy capital investment.
Early prototype devices compatible with standard fab production but with a much lower cost-of-error relieve the heavy burden on simulation and testing in favor of earlier device manufacturing and system analysis. The advantages of real devices vs. simulation are quite obvious:
- Device testing is much faster than computerized simulation.
- Working devices test the behavior of the integrated system, while simulation is usually effective for evaluating the device performance alone.
- Simulation cannot always predict how a system will function in real-time.
- Working devices allow proof of concept, which simulation cannot provide.
- Working devices allow development of the system software at a much earlier stage.
- Working devices uncover hidden bugs which simulation may not detect at all.
- Simulation depends on models, which are not always readily available for newly introduced devices.
High performance CPLDs and FPGAs (4) may also be effective tools for prototyping or emulation. FPGAs are a good solution unless high performance (in speed or gate-count) or high volume are an issue. Using FPGAs for designs which exceed their capabilities requires splitting the design into several devices. If high volume production is later required, re-engineering for production is costly; significant changes in performance are to be expected.
References
- 1) L.Kuhn, S.E. Schuster, P.S. Zory, G.W. Lynch and J.T. Parrish, IEEE Journal of Solid State Circuits , Vol.10, p.219 August 1975. (back to article)
- 2) A.R. Thryft, "ASIC designers take the chip express to production," Computer Design, July 16, 1990. (back to article)
- 3) M. Janai, "Technologies for Economic Production of ASICs," Solid State Technology, Vol.36, pp.35-38, March 1993. (back to article)
- 4) S.D.Brown, R.J.Francis, J. Rose and Z.G.Vranesic, Field Programmable Gate Arrays, Boston: Kluwer Academic Publishers, 1992, Ch.4. (back to article)
About the Author (back to top)
Meir Janai meir@chipx.com joined Chip Express (Israel) in 1986 as the Chief Scientist. Prior to joining Chip Express, Janai worked for Kulick And Soffa Industries (Israel) in a few positions including R&D Engineer and Director of Quality Assurance. Dr. Janai is serving as a member of the Israel's National Committee for R&D in Microelectronics. Janai earned his B.Sc. degree in Physics and Mathematics at the Hebrew University, Jerusalem. He received his M.Sc. degree, Cum Laude, and his D.Sc. degree in Solid State Physics at the Technion IIT, Haifa (Israel).