Parametric Testing to Improve Semiconductor Yields

Keithley Instruments, Inc.am Merkel, <%=company%>

Table of Contents

• "Yield or Perish"
  
• Where Parametric Testing is Used
  
• Linking Device and Process Parameters is Crucial
  
• Process Control vs. Device Reliability Monitoring
  
• Test Structures and Algorithms Require Fine Tuning for High Throughput
  
• Hardware and Software Issues
  
• Expanding Use of Parametric Testing

Parametric test systems often operate in cleanrooms, automatically collecting IC electrical data that can be related to process variables.
Photo courtesy of Keithley Instruments.

"Yield or perish!" could easily be the motto of semiconductor fabricators. Fabs can lose from $1 to $8 million in earnings for each percentage point of yield loss, depending on the type of IC produced. Designing and controlling processes to hit a yield target is almost a religion in the semiconductor industry, but it is not easy to practice (Figure 1).

Figure 1: Semiconductor yield is variable and caused by batch processing errors, such as missing or repeating processes, out of tolerance parameters or undetected interaction effects.

Cleanliness is next to godliness. For years, yield improvement efforts focused on contamination reduction. However, as further investments produce diminishing returns, fabs are directing their attention to process errors and interactions. Up to 25 percent of yield loss comes from device parameters.

While it hasn't yet attained the religious following of contamination control, the importance of parametric testing is growing rapidly. Most fabs use it in both product/process development and production testing to help reach, maintain or improve yields. This growth is largely because:

• Fabs must now control thousands of process variables, creating more opportunity for adverse interactions
• Many process variables are sensitive to very small changes and require tighter control
• Growing wafer sizes require tight control of process variables over larger wafer areas.

Transistor channel length is perhaps the most striking example of the effect a device parameter can have on yield. At the 1997 SPIE conference, Motorola's John Sturtevant reported that each nanometer of length variation reduces the operating frequency by 1 MHz. Each 1 MHz in frequency loss cost his company $7.50 in lost revenue on each IC, due to lower pricing.
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Where Parametric Testing Is Used
Parametric testing is performed after metal has been laid down on the wafer, allowing probes to make electrical contact with special test structures. The test structures, proxies for actual devices, are designed to allow fast data collection and diagnose production processes. Figure 2 shows a typical MOSFET test structure. Other types of test structures include diodes, capacitors, resistors, bipolar junction transistors, insulation (oxide layers) and conductor (metallization) structures.
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Figure 2: Typical MOSFET cross-section with parametric test probe areas shown. Measurements made during probe touch-downs include threshold voltage, I-V characteristics, series resistance, gate leakage current, and channel length/width.

Linking Device and Process Parameters Is Crucial
Useful parametric testing depends on a cause-and-effect link between electrical test parameters, process variables and yield. Establishing this relationship requires close cooperation between IC designers, process engineers, device integrators and test engineers.

Table 1 shows the interactions between various front-end process parameters and test parameters for typical CMOS devices. This table applies quality function deployment (QFD) (See footnote) techniques to quantify the relations between process parameters and device parameters. Each row represents an important process parameter and each column a device parameter. Each cell in the matrix ranks the correlation between process and device parameters: a circle with a dot signifies strong correlation; an open circle is medium correlation; a triangle denotes weak correlation.

Table 1 is generic, based on a cross-section of CMOS fabs. Fab engineers must develop quantitative relationships for their products and processes. Some use weighting techniques to calculate numerical values that describe the strength of correlation. This task is well worth the effort since the table then clarifies the objective of testing and can be used to establish parametric test suites for different phases of development and production.

Since each phase of a product cycle has different test needs, establishing sampling and test plans is one of the most important uses of the relationship table. For example, during product development, the number of wafer test structures and parameters measured may be as high as 1000, and testing a single wafer might take as long as 12 hours. For process qualification, this might drop to 250 parameters measured at 5 to 20 sites on the wafer. When production starts, perhaps only 100 to 200 parameters are measured at 3 to 5 sites per wafer. Table 2 shows a typical suite of CMOS production tests.
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Table 2: CMOS Production Tests
Test	Description	# in Test Program	Meas. Level
Opens	Test for open pads	2
Gshorts	Test for shorted gates	1
Gateleak	Measures gate leakage	2	1 pA
Ids	Drain current with known gate, drain, and substrate voltages	16	20 mA
Vtlin	Threshold voltage using maximum transconductance slope	22	0.4 - 1 V
Vtsat	Threshold Voltage in saturation	16	0.2 - 1 V
Idoff	Device leakage in off mode, drain to source	20	5 - 100 pA
Rds	Vds / Id at specified Id and Vgs	20	25 - 100W
Subvt-slope	Sub-threshold slope of drain current vs. gate voltage	20	< 10 pA
Peakisub	Peak substrate current	6	5 mA
Bvdss	Breakdown voltage from drain to source, gate grounded to source	10	10 V
Pfieldvt	Threshold voltage of a device with field oxide as the dielectric	2	12 V
NFieldvt	Threshold voltage of a device with field oxide as the dielectric	6	12 V
res2t	Determine resistance value using 2 terminal connection	21	2 - 1 kW
Isolation	Tests isolation leakage	11	100 nA
Diode fvmi	Diode characterization, force a voltage, measure current	2	10 nA
Diodebv	Diode breakdown voltage	2	3 -10 V
res4t	Determine resistance value using 4 terminal connection	11	2 - 1 k W
Totals		190

Process Control vs. Device Reliability Monitoring
There are two main types of parametric test, those used for process control monitoring (PCM) and those used for wafer level reliability (WLR) testing. Most current parametric testing is concerned with PCM to maintain or improve yields. PCM testing gathers data showing how semiconductor devices perform immediately after a set of process steps. Stimulation of the device under test (DUT) takes place without stress.

Neither PCM nor WLR testing will directly identify process interactions, but by measuring electrical parameters they can detect when interaction effects become important. In effect, parametric test data integrates the results of a set of process steps leading up to the point where testing took place, in so far as those processes affect device performance or reliability. Parameter variation could be due to any of the steps. The relationship table can help interpret the source of these variations and provide a common ground for all engineering disciplines in the fab.

As an example of PCM, consider test results that show a large variation in threshold voltage (Vth in Table 1,) but only moderate change in transconductance (G_m) or drive current (I_dsat) Given this data and a good relationship table, we would not suspect the implant in lightly-doped drain (LDD) region nor oxide thickness as the source of the problem. The most likely source of the problem would be channel implant or change in channel length (delta L) Examining the parameters for junction capacitance (C_j) in Table 1 would eliminate one or the other. A channel length problem is most likely associated with microlithography steps, whereas the channel implant would be associated with implant steps.

Similar analyses can be applied to WLR testing, a statistical process control tool used to identify process anomalies that could degrade parameters over the long-term. WLR testing applies a high level of stress to the test structure, sometimes taking it to the point of failure. Results can identify sources of anomalous variation in the process.

Once a statistical signature is established for qualified material, any change in the WLR test results indicates a change in the materials or microstructures. While these changes may or may not impact IC reliability, they show that material currently being manufactured is not identical to the material and processes that were originally qualified. The engineering team can then determine if the change warrants further investigation.

Overetching of polysilicon combined with a slightly abnormal implant dose in the LDD region (Figure 3) provides a good example of interaction effects that can be uncovered with WLR testing. If a production lot has an LDD length on the high side of its normal distribution (i.e., a thick sidewall spacer), or an LDD implant dose below the mean, CMOS devices tend to perform better on a hot carrier test.

Figure 3: The LDD region of a MOSFET reduces the electric field at the drain, which reduces adverse hot carrier effects. However, other process anomalies can interfere with the ability of the LDD to do its job.

Now consider another lot with the same degree of overetch, but in which the LDD length is at the low end of its distribution and the LDD implant dose is at the high end. The lot could perform poorly on a hot carrier test, even though each parameter is within its acceptable data distribution. An analysis of the relationship table will uncover the origins of this problem, so a process engineer can take such corrective action as tightening control on one or more process steps.
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Test Structures and Algorithms Require Fine Tuning for High Throughput
Automatic parametric test (APT) algorithms and test structures are intimately tied together. Fabs increasingly rely on the APT system manufacturer to supply both algorithms and structure designs based on information from the fab. Also, some fabs now share structure designs with each other when there is no direct competition.

Besides collecting useful data, a good test structure has a small footprint. Often, the structure is placed in the scribe lane on the wafer. Sometimes, this is difficult because the structure may require devices larger than those used in the IC in order to get a measurable signal. The trick is to create a structure that fits within the width of a scribe lane (typically, about 100 to 150 mm) and produces a measurable signal with a direct relationship to one or more process parameters.

Test structures are refined as the algorithms for the APT system are developed. Maximizing test throughput is a major goal in this part of the test development process. Some companies and vendors are exploring test structure designs that allow several tests to be performed simultaneously. Others are exploring ways to minimize pad space and prober movement by using structures in an addressable array. In any case, algorithms must be fully documented and correlated to test results from bench instruments before use on process lines.

Parametric test programs are developed from these algorithms. After establishing the relationship table with other engineering groups, a test engineer should understand the significance of each parameter, as well as target values and limits. Then differences between the target and measured values must be resolved before releasing a test program. The test engineer often establishes a set of "standard" wafers used to quickly check the test system and program for integrity. Typically, the test program includes documentation comparing expected and measured results, correlation and gauge study reports, and standard wafer test results.
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Hardware and Software Issues
A typical APT system consists of control electronics, source and measurement units, a switching matrix, signal amplifiers and a probe card that mates with the wafer prober. (See Figure 4) Sub-system arrangement and other design details have a large impact on APT throughput. Instrument settling time is a major issue, particularly when making low level capacitance and current measurements. For example, see the number and sensitivity of I_doff measurements in Table 2.

Settling time will become still more important as semiconductor devices increase in complexity and there is continued shrinkage in dielectric thickness and gate lengths. Currents and second order effects previously considered inconsequential are now becoming crucial, particularly in measurements of transistor off currents - including gate induced drain leakage (GIDL), drain induced barrier lowering (DIBL) and stress induced leakage current (SILC) - and dielectric absorption effects. Low current sensitivity is especially evident in DRAM, flash RAM and high speed logic devices. In battery-powered systems, even low levels of leakage are a problem if a large percentage of a die's transistors are affected.

The solution is an APT system designed for more sensitive measurements in a shorter time. Eliminating cabling between the probe card and signal amplifiers reduces parasitic capacitance. (The higher the parasitic capacitance in the signal path, the longer the settling time or the lower the accuracy for a given time.) Dielectric absorption, which has effects similar to parasitic capacitance, can be reduced by avoiding organic-based insulation (with the possible exception of Teflon). Supplying a signal amplifier for each probe pin ahead of the switching matrix further improves accuracy by allowing the matrix to process high-level signals.

As noted earlier, test algorithm design affects measurement speed. Another software feature that affects throughput is the sampling scheme. Most older APT systems require all wafers and wafer cassettes for a given test regimen to be tested the same way. Some of the newer software provides intelligent sampling, allowing wafers and wafers sites to be tested in different ways. More time-consuming tests, such as Q_bd (charge to breakdown) can be measured on only one location per wafer, while other tests are done at five locations on the wafer.
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Expanding Use of Parametric Testing
During start-up, parametric testing supplies as much as 80 percent of the information needed to achieve, improve and maintain yields. Typical applications are listed in Table 3. Both PCM and WLR test results can help solve a wide array of process related problems. Fab engineers don't need to be reminded of the axiom, "Yield or perish!" They experience it every day.

Table 3. APT Implementations
Development Activities	Production Uses
Materials characterization	Lot acceptance
Achieving final design rules	Maverick wafer/lot disposition
Characterizing process interaction during circuit design validation	Process transfer to another line or location
Qualifying processes for release to production; variation studies	Quality improvement - SPC and ISO-9000 applications
New equipment qualification	Yield enhancements

About the Author
William Merkel is a Senior Market Development Manager for Keithley Instruments, Inc. and currently directs APT hardware and test structure development. His seven years of experience with Keithley includes application engineering and other marketing assignments, all in the semiconductor test area. Previously, he was with National Semiconductor for three years in their Advanced Linear Test Engineering Group. Merkel received his BSEE degree from Youngstown State University.

For more information:
Keithley Instruments, Inc., 28775 Aurora Road, Cleveland, OH 44139-1891. Tel: 800-552-1115. Fax: 440-248-6168.

product_info@keithley.com

Footnote:
Quality function development is a systematic approach for decision making applied to product development and other activities which ultimately affect product quality. For semiconductor products, it mathematically relates process control requirements to device design characteristics, as measured through electrical parameter sampling.
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