Modular Process Technology for ASIC and System-on-a-Chip Design
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Samsung Semiconductor announced worldwide availability of its next generation ASIC family based on a 0.25µ modular process technology. This ASIC family provides up to 8.2 million usable gates at five layers of metal and includes customer-owned tooling (COT), STD110 (standard cell), MDL110HS (Merged DRAM and Logic-high-speed), MDL110LP (low power), MFL110 (Merged Flash and Logic), and MSL110 (Merged SRAM and Logic).
The modular process lets core-based system-on-a-chip (SOC) designers start with the logic process and then add DRAM, SRAM, and mixed-signal layers, or they can replace the DRAM with Flash memory. Samsung used a cell optimization technology that offers two sets of 0.25µ libraries. The first library is aimed at consumer products such as cellular handsets and global positioning systems (GPS) as well as notebook graphics acceleration. This library is optimized for low power consumption, moderate performance, and moderate gate count. The second library is targeted at networking, I/O subsystems and high-end desktop systems requiring higher performance, high gate count and moderate power consumption. Samsung plans to migrate to a 0.18µ process technology in 1999.
SOC designers can choose from a menu of fixed DRAM macros. Operating modes include EDO or synchronous DRAM. Memory configurations are available based on the amount of granularity required-densities up to 128Mb and word widths of x4, x8, x16, x32, x64, x128, x256, x512, x1024. With pin-out restrictions removed, very wide on-chip buses can be used to rapidly move data from function to function. This allows more efficient system operation and yields higher system performance without the need for a large external bus. Customized DRAM functions can be added as well. For instance, Samsung has created an innovative DRAM macro called SuperRAM that embeds a multiport cache SRAM. Designers using Samsung's MDL110 technology can achieve a data bandwidth of up to 17.0 G per second.
Samsung's modular ASIC process is driven by the fabrication of the 21164 Alpha microprocessor clocking in at 750MHz. The process uses five layers of metal with a sixth layer used for chip interconnect. It features operational voltages of 2.5V to 3.3V with 3.3V/5V standard and dual oxide enhancement for true 5V I/Os. Samsung's 0.25µ ASIC process is based on a 5 metal salicided dual gate and S/D. The STD110 features 1 poly, 5 metal plus an additional poly for analog; the MFL110 uses 2 poly and 5 metal, while the MDL110 uses 4 poly and 5 metal. A dual gate oxide is used to achieve both high and low voltages.
The performance of Samsung's 0.25µ technology is optimized through its use of a salicided dual gate oxide process. The transition from 0.35µ to 0.25µ yields an 83% power reduction for the MDL110LP at 1.8V and 47% power reduction for the MDL110HS at 2.5V. The MDL110LP's propagation delay at 1.8V is similar to its 0.35µ counterpart at 3.3V, while the MDL110HS is 35% faster at 2.5V. The MDL110SD at 27,000 usable gates per square millimeter increases gate density by 169% and the MDL110LP at 37,000 usable gates per square millimeter increases gate density by 230% as compared to the 0.35µ ASIC process. Samsung's local interconnect technology and stack via up to metal five are some of the key factors that permit the improvement in packing density. Using an aluminum-copper interconnection and a chemical mechanical polishing (CMP) maximizes process reliability.
Two sets of libraries are available for either high performance 2.5V or low power 1.8V applications. High performance applications include communications, networking, desktop PCs, and servers. Low power applications include portable computing and consumer products. These and other high-performance SOC applications require the strengths of Samsung's Intelligence-On-Silicon: lower cost, maximized bandwidth, and minimum power dissipation.
Samsung's hierarchical core-based design flow minimizes design cycle time and offers better circuit timing and performance predictability at pre- and post-layout. Samsung's design environment supports a portfolio of leading EDA tools: logic simulation, synthesis, floor-planning, test generation, static timing, RC analysis, fault simulation, power analysis, and formal verification.
Samsung provides an advanced user friendly graphical user interface (GUI) that eases system design, as a front-end to design software from the industry's leading tool vendors. Supported third-party tool vendors include Synopsys, Cadence Design Systems, Viewlogic Systems, Mentor Graphics, Avanti, System Science, and IKOS Systems. Samsung also provides a strong Design for Test (DFT) and manufacture capability that features compiled memory BIST and MDL BIST, SCAN/ATPG, JTAG, IDDQ, and a core test methodology. Samsung provides customer support at every phase of the design cycle through its worldwide design centers.
Several packaging options are available including high pin-count PQFP, TQFP, PBGA, TAB, COB, flip chip, chip-scale for consumer products, and C4 for high performance, high pin count designs. Packages are developed internally at Samsung and through partnership with Anam. To support high volume applications, Samsung continues to expand its portfolio of packaging offerings. C4 is the latest member of Samsung's packaging portfolio.
Samsung Semiconductor, Contact: Farzad Zarrinfar, 408-544-4555.