MatrixOne Delivers Methodology Kit For Collaborative Digital Semiconductor Design

Westford, MA -- MatrixOne, Inc. announced a new methodology kit that simplifies collaborative development of complex digital semiconductor designs. SITaR - which stands for Submit, Integrate, Test and Release - intuitively guides distributed project teams through the steps that are required to partition large scale designs into modular components that can be concurrently developed and then integrated, tested and released.

This methodology enables semiconductor design teams to manage their entire project including front-end design components such as RTL and software modules, back-end layout components, test harnesses, documentation and other design deliverables in a single configuration management environment. It enables each component to be independently designed and developed while the chip integrator assembles the design for test and release. It allows each team member to maintain versions of their work, track issues and report status.

The MatrixOne SITaR Methodology Kit is an add-on component for the MatrixOne Synchronicity Developer Suite. SITaR builds functionality directly into Developer Suite, allowing hardware or software blocks to be integrated, tested and approved in a flow that is intended to save time and reduces errors.

"SITaR crystallizes years of experience working with our leading-edge electronics customers to define world-class business processes for hardware/software co-development," said John Fleming, senior vice president, Industry Products and Solutions. "A highly repeatable and scalable methodology is critical to achieving the schedule compression required to gain a competitive advantage in today's fast-paced electronics market."

Developer Suite bundles together MatrixOne Synchronicity ProjectSync, a solution which raises design predictability with multi-site project and issue tracking and communications with MatrixOne Synchronicity DesignSync, a solution which boosts productivity by making design data available to the entire project team in a safe and managed manner, no matter where they are located. The optional Hierarchical Configuration Manager provides a block-based data management capability enabling hierarchical system-on-chip (SoC) design and reuse.

SOURCE: MatrixOne, Inc.