Lam Looks at Etch Roadmap

Lam Research Corporationtransition from 200mm to 300mm wafers, once viewed as critical for semiconductor industry productivity, has slipped into the background as industry conditions have deteriorated. Equipment companies who were leading the way just a few months ago are retreating just as quickly. Yet work goes on behind the scenes. No one wants to build the last 200mm fab, and the current slowdown threatens to push new construction into the 300 mm window. Equipment development efforts are continuing in anticipation of a sudden jump in demand.

For instance, according to Dave Hemker, <%=company%> (Fremont, CA) director of new etch product development, the company's 300mm plans haven't changed. Lam is working with customers on demos and joint development projects to get processes ready. The original schedule for the transition didn't allow time to qualify device-specific processes. Delays have created room for process optimization before the tools reach the pilot line.

Hemker expects 300 mm wafers to enter production at 0.13 or 0.15-µm feature sizes. While he doesn't expect much 200 mm manufacturing at 0.13µm, a few companies might shrink to that feature size on existing 200 mm lines. Such aggressive shrinks aren't surprising. Since larger wafers improve productivity, but don't change the process capabilities, the change doesn't make sense unless a company needs capacity. In contrast, shrinks are needed to stay on the technology curve. Chip companies want to adopt new device generations as soon as possible, but want to delay fab construction as long as possible.

By the end of next year, chip makers who are serious about 300 mm will have selected equipment for pilot lines opening in 2000. That timetable sets a deadline for equipment companies and, Hemker said, gives Lam a chance to differentiate itself from competitors. Continued investment will help Lam's 300mm products mature, while competitors who have pulled back won't make any progress.

Etch companies are also facing several changes in process technology. The most radical of these, the switch from etched aluminum metallization to dual damascene aluminum or copper, replaces metal etch steps with oxide etch. While metal etch is unlikely to disappear—smaller device manufacturers may not need dual damascene—it will become a small niche. Fabs have never liked metal etch or the complex in situ strip and passivation processes needed to avoid corrosion and particle generation, Hemker explained. Still, dielectric etch is not easy. Each of the several different implementation schemes for dual damascene has different requirements. For instance, etching the via first creates features with aspect ratios of 8 or 10:1, compared to the 4 or 5:1 ratio normally encountered. It's not yet clear which scheme is best, but Lam has achieved good performance with a two-step etch and nitride stop layer. Most other published results use a similar scheme. Nitride capacitance and overlay errors are the biggest problems with this approach.

Resist selectivity is especially important for these high-aspect-ratio etch steps. In the past, each new resist generation, regardless of chemistry, has used thinner, softer layers than its predecessor. Hemker expects this trend to continue, with lithography needs forcing changes in etch processes. Etch suppliers will need to pay more attention to differences between resist erosion in the bulk and faceting at corners and edges. Hard mask layers may be needed to protect the underlying materials. These changes can yield substantial benefits, though. Improved feature definition by the etch step expands the process window for lithography. Larger process windows reduce or delay the need for expensive resolution-enhanced photomasks.

After oxide replaces metal etch, new materials are on the horizon. Logic vendors need low dielectric constant (k) materials to reduce crosstalk and capacitance delays (see related article). Memory suppliers need high-k materials to maintain storage cell capacitance as the size of the cell decreases. Lam Research Corporationoutlook for etching of low-k materials is difficult to discuss, as the number of candidate materials is still quite large. Many candidates are carbon-based polymers, as is photoresist. Achieving good dielectric:photoresist selectivity will require novel chemistries. Low-k dielectrics aren't intrinsically more difficult to etch than oxide, Hemker explained, but less is known about their behavior.

At the other end of the spectrum, high-k materials have been in research and development for several years. Candidates include Ta₂O₅ and ferroelectrics like (Ba, Sr)TiO₃ for the cell insulator, and refractory metals like platinum and iridium for the cell electrode (see a related article). These materials often have non-volatile etch products, presenting problems similar to those encountered in copper etching. As Hemker told Semiconductor Online, it's not yet clear when high-k materials will see volume manufacturing. Three-dimensional cell structures may delay the transition until the 4 Gbit generation, expected to reach production in 2006. Lam Research Corporationsemiconductor industry has been described as a "no-limit poker table". For etch, as for other process steps, making radical technology changes during a slowdown raises the ante and may force some companies to step away from the table. But for the time being, at least, Lam Research plans to play out the hand.

By Katherine Derbyshire