Inovys Introduces SpeedScan And SpeedMap Analysis Tools For Semiconductor Devices

Pleasanton, CA -- Inovys Corporation introduced SpeedScan and SpeedMap, the latest addition to the Inovys suite of Design For Test (DFT) analysis tools for advanced semiconductor devices. A combinational toolset, SpeedScan and SpeedMap use AC Scan techniques for identifying path delay and transition delay faults on complex System On Chip (SOC) devices. These new tools enhance customers' ability to analyze device performance by individual circuit element, achieve device performance characterization using AC Scan, and to identify and diagnose design problems faster.

New complex SOC devices using nanometer processes exhibit more than simple stuck-at fault models. AC Scan patterns are being deployed in both engineering and production for at-speed testing. However, identifying the source of speed related problems on devices that contain millions of gates continues to be a challenge for engineers. SpeedScan and SpeedMap enables datalogging from inside the device, yielding timing performance information about the logic behind each and every flip-flop in the scan chain. Therefore, the challenge of resolving speed related problems is significantly simplified.

"Keeping pace with Moore's Law continues to challenge our customers," said Colin Ritchie, vice president of marketing, Inovys Corporation. "SpeedScan and SpeedMap are powerful tools for design debug and device performance analysis which helps our customers meet these challenges. This enables customers to complete the design validation of their leading-edge devices faster, which accelerates their time to volume production."

SOURCE: Inovys Corporation