Flash Memory Test System

The T5371 is a 70MHz test solution for flash and DRAM memory devices. With lower cost and more test coverage as the goal, the system is designed for both wafer probe applications with redundancy processing and flash logic intelligence. The at-speed fourth generation of the company's memory redundancy processor (MRA4) and added flash redundancy features enable the system to achieve new levels of wafer sort productivity.

With flash and DRAM devices now requiring double data rate capability and increased logic coverage for protocol logic, the system's Algorithmic Pattern Generator provides both NAND Palette Generation and full DDR capability to provide a one-pass, at-speed solution for flash probe and package production.

Protocol and DDR DRAMs complicate timing and pattern generation. The system's ALPG's Packet Generation, timing on the fly and true double data rate capability address test requirements of these new devices.

The system performs at-speed DDR flash, because of its true independent double data capability. Coupled with Timing-on-the-fly and the Cycle Palette of the Algorithmic Pattern Generator, this ensures fault coverage for package and Known Good Die applications.

The system also has Write Inhibit and pulse count capability and High Speed Erase Functional capability even during maximum parallel test applications. The APLG can generate Logic Vectors, DRAM interface logic, and Packet Coding for testing protocol devices during core test inserts and wafer test.

The system's software platform is compatible with the company's T533X and T5500 series ATL test systems, and has fixture compatibility to the T5336 systems for manufacturing leverage and porting of production environments to the new 70 MHz capability.

Advantest America, Inc., 3201 Scott Blvd., Santa Clara, CA 95054. Tel: 408-988-7700. Fax: 408-988-3950.