San Jose, CA -- The Fabless Semiconductor Association (FSA) announced the release of the FSA Mixed-Signal/RF SPICE Model Checklist, which provides fabless mixed-signal (MS)/RF designers using foundry SPICE models with consistent data to make foundry process and IC design decisions.
The Checklist streamlines the MS/RF SPICE model extraction and distribution process throughout the semiconductor supply chain including foundry, fabless, electronic design automation (EDA), intellectual property (IP) and design service providers. The Checklist helps designers obtain a better understanding of the source data, measured devices, completeness and quality of a model before using it to design ICs.
FSA's MS/RF Foundry Subcommittee developed this new Checklist as a follow-on to the FSA PDK Checklist introduced in March 2004, as SPICE Modeling is a major component of a PDK.
The Checklist consists of three sections:
- Process overview, contact information, foundry source document references and listing of supported circuit simulators.
- Model classification, general extraction information, model validation procedures, statistical variation, and summary/inventory of measured versus simulated results plots.
- Device-specific data divided into active (MOS, BJT) and passive (diode, varactor, inductor, capacitor and resistor) extraction and models.
"The Checklist is both foundry and EDA vendor-neutral and serves as a 'nutrition facts label' for foundry SPICE models," said Ken Brock, chairman of the FSA MS/RF Model Working Group and vice president of marketing at Silvaco. "IC designers' increased trust in foundry SPICE models from clear and consistent quality metrics will help to grow the overall market for MS/RF wafers purchased by fabless and fab-lite companies."
Companies contributing to the Checklist development include: 1st Silicon; Agere Systems; Agilent Technologies Inc.; AMI Semiconductor; Cadence Design Systems, Inc.; Exar Corporation; IBM; IMEC; Jazz Semiconductor; LSI Logic Corporation; Medtronic, Inc.; Mindspeed Technologies, Inc.; PMC-Sierra, Inc.; Polarfab; QUALCOMM Incorporated; Silvaco; Tower Semiconductor Ltd.; TSMC; UMC and X-FAB Semiconductor Foundries AG.
"The Working Group identifies common issues shared throughout the semiconductor supply chain in the development and use of SPICE models with a focus on RF and mixed-signal," said Paul Kempf, chairman of the FSA MS/RF Foundry Subcommittee and chief technology and strategy officer of Jazz Semiconductor. "By enabling the Checklist development, FSA has exhibited its dedication to supporting consistent best practices of design kits and models."
FSA's vision is that by the end of 2005, participating foundries would deliver a completed Checklist with each new SPICE model, benefiting fabless IC designers. The Checklist, a user's guide and a definitions/taxonomy document for all modeling terms can be downloaded free of charge from FSA's Web site.
FSA will host a technical session discussing the Checklist on Thursday, August 11, 2005 from 10:00 a.m. to 11:30 a.m. at the Westin Santa Clara. This session is part of the FSA Distinguished Speaker Series and Expert Roundtable.