Dual Gate Process

Many wafer manufacturers are creating devices containing dual gate structures. These structures contain gate areas with varying oxide thicknesses (see Figure 1 on back). Different gate oxide thicknesses are used to compensate for the various operational characteristics of each gate. Requirements for chip current can vary according to transistor function. Gate oxide thicknesses specifically designed for each function make the devices extremely efficient. However, this increases the complexity of the manufacturing process.

To create dual gate structures, wafers go through a sequence of cleaning, etching, masking and stripping steps. The exact sequence depends on the device design and the individual process of record for every manufacturer. Resist-strip steps will be performed at certain times (generally with sulfuric acid mixtures). Critical etches may also be performed – a portion will be masked etches requiring BHF solutions while others require dHF. Finally, cleans will be required prior to and following the gate creations.

The various process steps required for dual gate applications result in numerous wafer movements between chemical tanks in open bath systems. These steps create lengthy process cycles. There is also a very high Cost of Ownership (CoO) associated with this application, particularly the BHF and sulfuric steps. CoO and the complexity of wafer movements are critical concerns in dual gate processing. The process performance of each individual step is also significant.

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