Co/Ti (cap) Silicidation for sub-0.25 µm MOS Technologies

Jan Wauters, IMEC, Leuven, Belgium

The scaling of CMOS processes below 0.25 µm forces a transition from TiSi₂ to CoSi₂ contacts. A new Co-silicidation process with a Ti-cap layer is very promising with scalability towards 0.1 µm.

Silicides, used as source/drain and gate shunt materials, exhibit metallic conduction and have a low sheet resistance. The selectivity of the metal reaction with Si over the reaction with SiO₂ is crucial in selecting a silicide material. The best silicides for MOS are TiSi₂, widely used in current production processes, and CoSi₂.

Scaling CMOS processes below 0.25 µm imposes problems on the silicidation module. The formation of TiSi₂ occurs in two rapid thermal processing (RTP) steps, with a selective etch in between to remove unreacted metal. In the first step, Ti reacts with Si to form the high-resistance C49 TiSi₂ phase, which then converts to the low-resistance C54 phase during the second RTP step. This transformation to C54 can become troublesome for narrow silicide lines. Narrow lines constrain growth of C54 nuclei in between C49 grains to one dimension. Transforming the narrowest lines to the low resistive phase requires higher temperatures.

CoSi₂ process

CoSi₂, which uses a similar two-step process, can be a viable alternative to TiSi₂ for feature sizes of 0.25 µm and below. In the first RTP cycle, Co reacts with the exposed Si to form the CoSi phase, with a specific resistivity of about 120 µW-cm. After wet etching of the unreacted Co, the reaction proceeds during the second RTP cycle to form CoSi₂ (typical resistivity of 16 µW-cm). Narrow feature sizes do not delay the nucleation of CoSi₂ from CoSi, so no linewidth effects on silicide performance are expected. For Co silicidation, the major concerns are sensitivity to cleaning and irreproducible yield on narrow lines.

Ambient contamination in RTP

Although Co is less reactive with the ambient and its contaminants than Ti, ambient contamination still plays a significant role in silicide reproducibility. In state of the art RTP the main contributor to ambient contamination is the wafer itself.

After wafer loading, the process gas flows through the chamber to purge impurities that entered through the open door (Figure 1). After the impurity level drops below a certain limit (e.g. 10 ppm), lamp heating is started and species begin to desorb from the wafer. This desorption peaks at the end of the temperature ramp and decreases exponentially afterwards. System-induced contamination is usually very low; the wafer itself is the main source of contamination in the initial stage of heating. Impurities can desorb from the field oxide regions, the spacers, the silicon areas, the deposited metal, and the backside of the wafer.

Figure 1 : Conceptual sketch of the concentration of contaminants in the N₂ ambient during RTP, designating the various sources of contaminant contribution.

Technological solutions: Co silicidation with Ti cap

One potential solution to this problem is Co-silicidation with a Ti interface layer. This technique induces high stress in the layer: the process window for acceptable lateral silicide growth and junction leakage is small. An alternative method, proposed by Digital (Maynard, MA), uses a TiN cap layer. Whereas Ti is very reactive, TiN is less reactive but is a good diffusion barrier.

IMEC has investigated the use of a Ti cap layer on top of Co to control desorption into the ambient. We compared oxygen levels in the RTP system for blank Si wafers, wafers with a thin Co film, with Co/Ti (cap), and with Co/TiN (cap) (Figure 2). Although the TiN cap reduces the final O level, it is not as efficient as Ti during the initial stage of the silicidation process. Similarly, we monitored the moisture level in the chamber for a wafer covered with TEOS oxide, one with Co on top of TEOS, and one with the Co/Ti (cap) stack on top of the TEOS layer. The Ti cap minimized the ambient contamination by reacting with any residual moisture in the chamber. (Figure 3)

Figure 2 : Oxygen concentration in N₂ ambient during a heat cycle of 550°C for 60 sec for (a) a Si dummy wafer, (b) a wafer coated with 20 nm Co, (c) a wafer coated with 15 nm Co / 8 nm TiN (cap), and (d) a wafer coated with 15 nm Co / 8 nm Ti (cap).

Figure 3 : Thermal desorption measurement in ppm of H₂O from (a) 350 nm of TEOS on Si, (b) 20 nm Co on top of TEOS, and (c) 15 nm Co with an 8 nm Ti cap on top of TEOS.

Edge thinning

Edge thinning effects are another important issue. At the very beginning of the second RTP cycle Co is the most mobile species and has to overcome any SiO₂ formation on top of the growing silicide. The SiO₂ layer forms by diffusion of O₂ or H₂O contamination through the Co to the silicidation front. Edge thinning of the silicide occurs when moisture adsorption and desorption from adjacent oxide regions encourage SiO₂ formation. The contamination comes from the wafer itself, rather than the ambient. A TiN cap, which behaves as a diffusion barrier; is deleterious instead of beneficial. Plan view SEM and measurement of the electrical linewidth loss (Figure 4) show that the width of the edge effect can be tuned by varying the composition of the TiN cap layer from almost pure Ti (left) to the standard TiN composition (right). No thinning was observed along the edge of CoSi₂ formed next to a SiO₂ area by the Co/Ti(cap) process (Figure 5). A (reactive) Ti cap layer avoids edge thinning and achieves good reproducibility of silicidation in narrow areas.

Figure 4: Sheet resistance and corresponding plan view SEM of Co-silicided 2 µm wide n+ active area lines for Co silicidation with TiN cap of which the composition varies from almost pure Ti (left) to standard TiN (right).

Figure 5: Cross-sectional TEM of a CoSi₂ layer formed from 15 nm Co / 8 nmTi (cap) along a field oxide.

Mechanical properties

Mechanical stress in excess of the critical shear stress on an active slip system generates dislocations and defects. When scaling down silicidation, the mechanical stress generally increases. We examined the mechanical properties of CoSi₂ and TiSi₂ down to 0.1 µm by micro-Raman spectroscopy combined with finite element modeling (FEM). The Ti-cap Co-silicide process generates significantly less stress than the TiSi₂ process and other CoSi₂ silicide processes. Although a Ti interfacial layer's effect on ambient contamination is similar to that of a Ti cap, the interfacial layer increases e stress formation in the silicide and in the Si underneath.

FEM simulations put a limit on the scalability of the Ti interfacial layer process beyond 0.25 µm. In contrast, the scalability of the IMEC Ti-cap CoSi₂ silicide process is guaranteed down to 0.1 µm.

Jan Wauters is a scientific editor at IMEC and responsible for authoring and editing the research organization's numerous company technical documents and publications. Wauters joined IMEC in 1996. Prior to that, he was a nuclear research scientist at University of Tennessee at Knoxville. Wauters earned his PhD from University of Leuven, Belgium.

For more information: Marianne Van den Broeck, IMEC. Kapeldreef 75 B-3001 Leuven, Belgium. Tel: 32-16-28-12-11, fax: 32-16-22-94-00.