Copper Technology Enables Metallization and Polishing Down to 0.035-Micron Generation
The Ultra ECP and the Ultra SFP will enable the deposition of copper interconnects on silicon wafers down to the 0.035-micron device generation and polishing of copper-integrated dielectrics with a value of 1.5, regardless of wafer size.
Both systems are capable of operating with manual loading of 200 mm silicon wafer cassettes or automated guided vehicle (AGV) loading of 300 mm wafers in minienvironment pods (SMIF or FOUP). Processing in the multiple stacked single-wafer chambers in both systems reduces the footprint of the systems. The processes are independent of wafer size, and meet current requirements for processing 200 mm wafers as well as the coming 300 mm wafers.
The Ultra ECP System provides the industry with the ability to electroplate copper on thin (<50Å) seed layers with excellent uniformity (<1% @ 1 Sigma) wafer-to-wafer and within the wafer, achieving these results on both 200 and 300 mm wafers. It assures a wide process window, starting at the 0.13 micron manufacturing node and extending to the 0.035 node and even beyond.
COO also is improved by a very small footprint, which is at least half the size of other plating tools now on the market, and the footprint remains constant with the transition to 300 mm wafers. The Ultra ECP is a stand-alone system which processes single wafers at a throughput of 60 wafers per hour through the use of multiple stacked chambers accessed by dual robot end effectors. The NT-based software and control system can be integrated with Intranet and Internet self-diagnostics and with SECS/GEM communications standards.
The system incorporates an in-situ film thickness uniformity monitor and control to assure uniformity of the film thickness, film quality and the gap-filling capability regardless of wafer size and even with different seed layers or final plating thicknesses. An automatic thickness profile-tuning feature speeds up the system tuning process and also reduces tool qualification time.
Fully compatible with the ECP process is Ultra SFP System, which is designed for copper integrated with low K dielectrics (from 3 to 1.8 or less) and provides the semiconductor industry with its first stress-free electro-polishing system with layer-by-layer atomic level control.
The Ultra SFP incorporates three polishing chambers and three cleaning chambers (including bevel and backside cleaning.) With a minimum remove thickness of less than 50Å and a remove rate of 0.1 to 0.5 microns per minute, the system achieves a throughput of 60 wafers per hour for 1.0-micron films.
The system's automated features include in-situ remove rate uniformity monitoring and control, end-point detection for the entire wafer, and compatibility with all industry automation needs including SECS/GEM, SMIF and AGVs.
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