CMP Grinds Toward Maturity
Chemical mechanical planarization (CMP), long derided as a slow, crude, unreliable, but unfortunately essential process, is slowly reaching manufacturing maturity. According to Wilbur Krusell, vice president of Lam Research Corporation's CMP division, customers are demanding, and receiving, integrated systems, ready to drop into production lines. In particular, new CMP applications demand better process control.
CMP was first used for oxide planarization. A conventional multilevel interconnect structure stacks wiring layers on top of each other, with oxide dielectric filling the gaps between lines and providing insulation between layers. The oxide topography varies as the oxide layer follows the underlying features. These variations accumulate from layer to layer. Meanwhile, more stringent resolution specifications have forced lithography systems to use larger numerical apertures, reducing the depth of focus. The combination of small depth of focus and wafer topography can be lethal. At best, the lithography process window is very small. At worst, it becomes impossible to focus the entire exposure field. Oxide CMP reduces this topography variation. As users grew more comfortable with oxide CMP, they began to use the process for other steps as well. For example, W-plug structures rely on a thick "blanket" of tungsten to ensure adequate filling of the high aspect ratio plugs. CMP then polishes the excess tungsten away, exposing the oxide intermetal dielectric for the next step.
George Canavan, vice president of marketing for Lam's CMP division, calls oxide and tungsten CMP "non-critical" applications. In these situations, CMP is used to remove a thick layer of material as quickly as possible. Removal rate is the most important measure of performance, and the structures are relatively unaffected by erosion and dishing. Critical applications are those, such as shallow trench isolation (STI) and copper damascene, for which CMP is an enabling technology. Damascene processing, used because copper is extremely difficult to etch, reverses conventional metallization. Rather than depositing oxide into spaces etched in metal, damascene cuts lines into the oxide, fills them with metal, then polishes the excess metal away. STI, which allows tighter packing of transistors than conventional isolation, deposits a blanket oxide over isolation trenches, then polishes the oxide back to expose the device regions.
Both damascene and STI place stringent limits on dishing and erosion, which introduce topography variations. Unfortunately, isolated features tend to polish more rapidly than dense features, as the entire force of the polishing pad is directed at a smaller area. The isolated features then tend to erode during the overpolish required by the dense features.
Large open areas tend to "dish", or be overpolished in the center. Adding dummy "fill" features reduces both these effects by minimizing pattern density variations, but such features may have electrical effects. Furthermore, Canavan told Semiconductor Online, chipmakers want to be able to use the same process for all layers in a structure, and all circuit designs.
Dennis Ouma and coworkers at the Massachusetts Institute of Technology examined pattern density effects in more detail in work presented at the recent CMP Multilevel Interconnect Conference (CMP-MIC). They found four key concepts:
- Polishing ar any point depends on the effective pattern density at
that point.
- The planarization length characterizes the length scale over which neighboring topography affects the effective density. That is, a feature is "isolated" when there are no other features within the planarization length.
- Each circuit layout produces a range of effective densities. Pattern density effects thus create a range of post-polish oxide thicknesses.
- Larger planarization lengths average topography more effectively, reducing the global thickness variation.
Thus, the group concluded, increasing the planarization length will reduce dishing and erosion. Lam's Teres system (see Figure) represents one potential solution to this problem. It uses a linear polishing belt running at 400 ft./min. Rotary polishers run at table speeds of 28 rpm and carrier speeds of 32 rpm, for approximately 100 ft./min. linear relative speed. Systems with lower polish speeds require higher pressures in order to achieve acceptable material removal rates. However, Lam claims, higher polish pressures increase pattern density effects.
The MIT researchers, examining oxide planarization of standard structures, found that the planarization length at conventional polish speeds was 3 mm, while high polish speeds achieved a 9.5 mm planarization length. They suggested that pad dynamic response may be an important cause of this dramatic improvement.
By Katherine Derbyshire