Chartered And Singapore's Institute Of Microelectronics Collaborate On Advanced Fine-Pitch Packaging Research
The research is based on the 65nm processes developed by Chartered and its joint development partners, IBM, Infineon Technologies and Samsung Electronics Co. In addition to enabling more choices, the Chartered-IME collaboration means designers could potentially benefit from silicon-proven solutions and modeling tools to characterize the impact of fine-pitch package on silicon early in the design development cycle, which should improve manufacturability and back-end-of the-line yield performance.
As the industry places increasing value on high-performance, power-driven system-on-chip products with a large number of input/output signal lines and interconnects, fine-pitch packages will require bump chip pitches below 180 micron. However, there is no manufacturing-worthy fine-pitch packaging solution today due to implementation challenges and the complex interaction between the silicon and packaging technology.
"Our collaboration with IME is aimed at developing industry solutions that give the semiconductor industry a silicon-proven fine-pitch packaging solution," said Dr. Liang-Choo "LC" Hsia, senior vice president of technology development at Chartered. "With the transition to 65nm, companies are realizing that having a successful backend packaging strategy is a key to realizing volume ramp quickly and meeting time-to-market goals. Chartered is committed to being a leader in research and development of solutions that support our customers in realizing superior and reliable results in partnership with a value chain."
To meet technically demanding requirements, the research will utilize a large die, copper/low-k test chip structure that has a fine bump pitch. The work will investigate the package-level reliability and optimize the performance against various fine-pitch packaging technologies. These include high-lead solder bump, copper posts and polymer encapsulation. Additionally, modeling tools will be built to capture the correlation between the fine-pitch packaging technologies and test structure stress levels, integrity and performance. Using the modeling results, the impact of under-bump metallurgy on low-k integrity and the compatibility of underfill materials with low-k structures will also be evaluated and characterized.
"The research collaboration integrates IME's proven expertise in back-end packaging know-how with Chartered's success in advanced copper metallization and low-k dielectric process manufacturing," said Professor Dim-Lee Kwong, Executive Director of IME. "We are excited with the opportunity to work together to resolve one of the industry's most challenging back-end integration challenges and provide our mutual customers with a reliable path from manufacturing to final chip packaging."
SOURCE: Chartered Semiconductor Manufacturing