Article: Implementation Of Wafer Level Parallel Test

By Randall G. Lee, Keithley Instruments, Inc.

Parallel parametric test is an emerging strategy for wafer-level testing that involves concurrent execution of multiple tests on multiple scribe line test structures. It offers a relatively inexpensive way to increase throughput, thereby lowering the cost of ownership (COO) significantly. Just as important, as device scaling increases the randomness of failures, parallel testing can address the growing need to perform more tests on the same structures in less time. In this case, users can choose to either increase the number of tests performed at each site, or increase the number of sites.