Multirate 8 Gb/s Embedded SerDes Core For ASIC Integration Introduced

Boeblingen, Germany -- Agilent Technologies announced the availability of a 8 Gb/s multirate embedded SerDes core for storage networking OEMs. The new SerDes core was validated in a 90-nm CMOS process and it supports 8, 4, and 2 Gb/s data-transfer rates. Due to the core's noise immunity, modular design and low power consumption, storage OEMs are now able to embed as many SerDes as needed onto a single ASIC chip.

In tests conducted at Agilent, the embedded SerDes ASIC achieved error-free transmission driving signals over FR4 material (at room temperature) a distance of 40 centimeters (about 16 inches). The SerDes core offers these industry-leading features:

• Decision Feedback Equalization (DFE)
• Automatic receiver DFE tuning
• BERT on chip for channel bit error rate optimization
• Signal eye diagram support built in
• LC-based oscillator for improved power-supply noise rejection
• 1149.6 AC-Extest for testing AC-coupled connections between ICs on the PCB
• Internal 100-ohm differential termination

Agilent's embedded SerDes ASIC development model provides support throughout the entire product life cycle. It incorporates testing capabilities as early as the definition of system-level architecture and accounts for in-circuit manufacturing test, functional test, system turn-on and debug, and field diagnostics. With this model, equipment manufacturers can develop high-bandwidth networking and storage systems.

SOURCE: Agilent Technologies