Articles
RSSIEDM: Evolution and revolution in transistor scaling
December 13, 2000
Evolving CMOS below 50 nm
It's a little more complicated than that, of course. The gate length dimensions were achieved using a two-mask phase shift mask approach with overexposure. Polysilicon line edge roughness was ± 5 nm. Chau declined to explain the "aggressive" scaling methods used to achieve sub-1.0 nm gate oxide thickness and sub-100 nm gate electrode thickness, but reported an inversion capacitance greater than 1.9 µF/cm2 for both p- and n-MOS transistors. The company claimed the gate delays, 0.94 ps for n-MOS and 1.7 ps for p-MOS, were the smallest ever reported for CMOS devices.
Retrograded wells, "aggressively scaled" source/drain and source/drain extension implants, and low (less than 1000°C) activation anneals completed the transistor structure. No halo implant was used. Ni silicide minimized contact resistance.
Leakage current is a major concern for ultrathin gate oxides. Chau reported on currents of 514 µA/µm and 285 µA/µm for n-MOS and p-MOS, respectively, with an 0.85 V drive voltage. Off current was at or below 100nA/µm, Chau said.
Though Intel's announcement grabbed headlines in the popular press, several other companies discussed their sub-50 nm devices at IEDM as well. H. Wakabayashi and coworkers at NEC Corporation (Kanagawa, Japan) used tilted channel ion implantation in their 45-nm and smaller CMOS transistors. To maintain a steep halo profile, the NEC group used a reverse-order source/drain process, activating the source/drain extension implant with a high ramp rate spike anneal after the deep source/drain formation. The researchers patterned the SiON gate dielectric using 248 nm lithography, augmented by point-source electron beam exposure. Cobalt silicide, formed at less than 700°C after the gate-sidewall formation, completed the devices. Wakabayashi described 24-nm n-MOSFETs with drive current of 796 A/m and off current less than 300 nA/m at 1.2 V.
C-P. Chang and coworkers at Lucent Technologies (Murray Hill, NJ) discussed a "self-aligned local-channel V-gate with optical lithography" (SALVO) process. The basic process flow uses only current production tools, but can be enhanced with high-k dielectrics, metal gates, or halo implants:
- Isolation and tub implants
- Nitride/pad oxide sacrificial gate patterning with KrF phase shift lithography
- Source/drain process (can be enhanced with halo implants, S/D extensions with regular spacers)
- S/D silicide
- Gate planarization with oxide CMP
- Nitride wet etch removes sacrificial gates, leaving pad oxide to protect the underlying Si surface
- (A pre-spacer local channel implant can be added here)
- Inner spacer formation on pad oxide by conformal nitride deposition and reactive ion etch, stopping on pad oxide. The width and channel length defined by the inner spacers are insensitive to variations in lithography and etch profile.
- Local channel implants(with rapid thermal annealing, if desired), aligned by the inner spacers.
- Pad oxide removal
- Gate oxide deposition (high-k dielectric or thermal oxide)
- Amorphous silicon deposition, ultra-low energy gate implants, rapid thermal annealing, and metal deposition create a V-shaped polysilicon/metal (or dual metal) gate inside the region defined by the inner spacers. The RTA step is performed with the silicide capped by oxide, with temperature less than 950°C.
- V-gate patterning by CMP or lithography and reactive ion etch.
- Back-end metallization
The radical approach: thin and vertical transistors
Other groups took a far more revolutionary approach to the transistor scaling problem. Jakub Kedzierski and co-workers at University of California, Berkeley (Berkeley, CA) fabricated thin-body transistors with silicide source/drains, no doping, and gate lengths down to 15 nm.
To build the body of the transistor, the Berkeley group thinned a lightly-doped silicon-on-insulator film to 140 Å, then defined a mesa with a G-line/electron-beam double exposure. A thermal gate oxide, polysilicon gate, and SiO2 hard mask completed the gate stack.
Kedzierski explained that large series resistance of the thin body layer has been a significant concern for thin-body transistor designs. To address it, the Berkeley group used low-barrier silicide source/drains. PtSi, with an 0.24 V barrier height, was used for p-MOS devices, while ErSi1.7 gave an 0.28 V barrier height for n-MOS devices.
The saturation drive current for these devices does not yet meet Roadmap specifications. Three methods are available to increase it, Kedzierski said: use a silicide with a lower barrier, reduce the oxide thickness, or add an extension doping to lower the barrier. Though extension doping provides a depletion layer at the source/body junction, it also requires a high temperature anneal. Undoped devices can be made below 400°C.
The remaining two papers in IEDM's sub-50 nm device session discussed vertical transistors. Vertical transistors use layer thicknesses to define channel lengths, avoiding the many difficulties of advanced lithographic techniques. However, as envisioned in papers presented at last year's IEDM conference, vertical transistors require different layer sequences for n-channel and p-channel devices. Contact to the components of the device is difficult at best, and design layouts require radical changes. One possible solution, presented by Thomas Schulz and coworkers at Infineon Technologies (Munich, Germany), nestles the channel against the sidewall of a silicon trench. In that location, it maintains electrical contact with the substrate. The source and drain regions are likewise electrically accessible.
Finally, Lucent Technologies (Murray Hill, NJ) announced a p-channel version of its vertical replacement gate design. The company discussed its N-channel VRG transistors at IEDM last year.
Katherine Derbyshire
Managing Editor, Semiconductor Online
| Click here to subscribe to the free weekly Semiconductor Online newsletter. |
