Articles
RSSAccelerate technology development with TDSRAM
January 22, 2001
New advances in semiconductor process technology have brought increasing complexity and development costs. Next generation technologies for new and improved tool platforms, coupled with new materials and processes, are responsible for marked increases in technology development costs. Rapid recovery of these expenses allows maximum profitability during the lifetime of the technology.
Contents
•Requirements for technology acceleration
•TDSRAM Design for Technology Development
•TDSRAM Analysis methodology for rapid process Optimization
•Summary
Early access to decision-quality information during technology development programs is often a key competitive advantage. Semiconductor manufacturers typically choose an SRAM vehicle for technology development and early yield enhancement activities. In many cases, however, such circuits can have significant shortcomings, particularly when designs are performance-oriented rather than optimized for technology development. Because accurate SPICE models are not available early in the process development cycle, re-mapping of IP-quality circuits to new technologies may induce circuit yield and functionality issues not solely associated with device and process limitations. These issues often delay technology development and yield enhancement schedules. This combined risk of schedule slip due to finite, multi-tasked design resources, coupled with functional problems not related to process/device issues, makes re-mapping of IP/product circuits a sub-optimal solution for next generation technology development.
The following discussion details a technology development SRAM (TDSRAM) which is suited to the needs of process integration and yield enhancement. It provides an effective means for risk reduction and for reduced overall development cycle times.
Requirements for technology acceleration
The 0.18 µm and smaller technology nodes require extensive tool and material characterization prior to full process development. Critical decisions such as stepper platform and OPC/PSM algorithms must be made early in the development lifecycle to minimize schedule delay and development costs.
After preliminary definition of tool and material platforms, design rules of the new process technology must be "windowed" thereby determining integration margins and process capability. These exercises minimize costly design rule changes late in the process development cycle. Preliminary device models must be characterized, optimized and published to the design community in order to ensure product readiness at the time of process certification. Finally, key yield limiting steps must be characterized and engineered out of the process flow while early reliability failure mechanisms are identified.
TDSRAM Design for Technology Development
TDSRAM uses a robust and highly versatile architecture that allows process capability learning, even if first-pass device models do not accurately reflect observed device characteristics. By using conservative design practices, the TDSRAM attempts to confine failure mechanisms to bitcell array regions of the circuit where defects may be localized, quantified and correlated to in-line defectivity data. Wherever possible, the design places circuit elements not requiring bitcell array pitch-matching in global periphery regions, and draws them to relaxed or nominal layout rules. Built-in diagnostic features de-couple array from periphery-logic failure mechanisms. For example, an analog port allows individual bitcells to be written/read in the event of an I/O or periphery logic failure. Effective isolation of failure events to bitcell array or peripheral circuitry regions expedites circuit debug, physical failure analysis, and ultimately process optimization.
TDSRAM's architecture is subdivided into functionally independent sub-arrays. These sub-array elements may be configured to characterize nominal design rules, design rule excursions or "pushed" rules, embedded memory bitcell designs, or OPC/PSM algorithms. Figure 1 uses unique sub-arrays within the overall design to evaluate a set of gate-poly OPC algorithms within the SRAM bitcell. This approach maximizes learning on a small silicon area while providing a realistic topology and statistically significant sample size for extracting process capability information. Alternatively, separate sub-arrays could use a suite of embedded bitcell options to help the process integration and design engineer evaluate and quantify cell design versus process capability tradeoffs.
Because TDSRAM is an automated design solution, rapid retargeting to new or modified design rules eliminates schedule delays that can occur in new technology test vehicle development. Auto-generation of pitch-matched elements within unique TDSRAM sub-arrays supports the rapid design cycle time required to meet the technology development roadmap.
TDSRAM Analysis methodology for rapid process optimization
While the circuit must extract process capability information, corresponding data analysis techniques must reduce raw data to decision-quality information. Predominant failure modes or bitmap "signatures" must be characterized and correlated to scribe-line parametric data and in-line defectivity data.
Bitmap analysis is often used for rapid identification of defectivity levels and primary yield and process issues. Figure 2 illustrates an example bitmap response from a TDSRAM sub-array designed to characterize nominal design rules at the 0.18 µm technology node. In this example, the bitmap response shows specific events including single and double-bit failures. Reducing raw bitmap data to pareto response charts quickly isolates dominant failure modes within the process flow (Fig. 3). Accurate interpretation of pareto response behavior can guide physical failure analysis activities (Fig. 4).
Evaluation and correlation of parametric data to primary bitmap failure modes can further expedite process debug using TDSRAM. Bitcell array-like parametric modules which emulate array topology but isolate one or several failure modes can help engineers assess the "health" of the silicon. Figure 5 illustrates the parametric response of two contact chain test structures designed within random logic and bitcell-array topology, respectively. The test structure built using bitcell array topology exhibits a failing distribution while no signal is observed in the random logic-like structure. By correlating test structure response to TDSRAM bitmap signature, failure analysis efforts can focus on key failure mechanisms and confirm root cause events (Fig. 6).
Summary
Using TDSRAM in conjunction with a comprehensive data analysis flow has not only helped define process margins in new technology development programs, but has accelerated first silicon yield, process stabilization, and process qualification. By using a robust and timing-insensitive architecture, TDSRAM eliminates functionality risks associated with performance-based designs while allowing technologists to characterize process capability on new design rule platforms. TDSRAM's greatest value is obtained with data analysis routines for bitmap analysis, bitmap correlation to parametric response, and bitmap correlation to in-line defectivity data.
Mark Craig is a Senior Technical Manager, SRAM Technologies for TestChip Technologies, Inc. in Austin, Texas. He is responsible for technical and business development for TDSRAM. His previous work experience was in Motorola's Advanced Products Research and Development Lab. Mark holds a BSEE from the University of Texas at El Paso and an MSEE from the University of Texas at Austin.